In many Dual In-line Memory Modules (DIMMs) that have Dynamic Random Access Memory (DRAM) devices coupled to them, there are general signal reflection issues on the data lines. Signal reflection occurs when a signal reaches the end of the signal line it is transmitted across and at least a portion of the signal then reflects back to the origin point. Signal reflection can be mitigated by changing the resistance in the line that transmits the signal. Signal reflection issues are magnified with a DIMM that has more than one memory rank because there is more than one load on each data (DQ) or strobe (DQS) signal. The signal integrity challenges are managed by using resistive termination in the various memory ranks, according to whether read or write cycles are occurring, and which rank is being accessed.
Recently, quad ranked (QR) DIMMs have become popular, which further magnifies the signal reflection issues due to four loads being on the data strobe and data signal lines. Fully Buffered DIMM (FB-DIMM) technology has led to the need for FB-DIMMs with four ranks. There are motivations to having four ranks on a DIMM.
First, in the case of the quad ranked (QR)×8 DIMM, there are four ranks with 9 DRAM in each rank, with a width of 8 bits per DRAM. These DIMMs have a major power advantage over the more traditional 36 device DIMM, the dual ranked (DR)×4, which has two ranks with 18 DRAM in each rank, with a width of 4 bits per DRAM. Since only half as many devices are being accessed on each read or write, the overall power of the QR×8 DIMM can be about 30% less than the equivalent DR×4.
Second, a QR×4 DIMM with 72 DRAM can have twice the capacity of a DR×4 DIMM. Large capacity per DIMM socket is valued by servers.
Third, a QR×4 DIMM built with 72 of the smaller devices (for example, a 1 Gb DRAM) can be much less expensive than a DR×4 or QR×8 DIMM of the same capacity, built with 36 of the larger devices (for example, a 2 Gb DRAM.) This is because the larger device might be 5-10 times more expensive than the smaller device, when the larger device is first available.
The JEDEC Specification for Double Data Rate 2 (DDR2) memory (Revision JESD79-2C, May 2006 by JEDEC Solid State Technology Association) brings the resistive termination on-die (on the DRAM device) and it is stated as On-Die Termination (ODT). By bringing the resistance on-die, the DIMMs are generally more configurable for different resistance values. ODT values are programmed into the Extended Mode Register EMR(1) per DRAM device. But the ODT value, corresponding to the resistance, is programmed by a Advanced Memory Buffer (AMB) device on an FB-DIMM and the AMB programs all ODT values on the DIMM uniformly. The JEDEC DDR2 Specification gives 4 possible values for programmable resistance: disabled, 50Ω, 75Ω, and 150Ω.
The main issue with signal integrity on an QR FB-DIMM with error checking and correction (ECC) is the ECC DRAM device itself. Unlike the non-ECC DRAM devices, the ECC DRAM device is generally located on the DIMM directly behind the AMB on the opposite side of the printed circuit board (substrate). These signal lines are extremely short compared to other DRAM devices and the AMB is located at the physical center of each signal trace, instead of at the end of each trace.